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| (R) DG441, DG442 Data Sheet November 20, 2006 FN3281.10 Monolithic, Quad SPST, CMOS Analog Switches The DG441 and DG442 monolithic CMOS analog switches are drop-in replacements for the popular DG201A and DG202 series devices. They include four independent single pole single throw (SPST) analog switches, TTL and CMOS compatible digital inputs, and a voltage reference for logic thresholds. These switches feature lower analog ON resistance (<85) and faster switch time (tON <250ns) compared to the DG201A and DG202. Charge injection has been reduced, simplifying sample and hold applications. The improvements in the DG441 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 40VP-P signals. Power supplies may be single ended from +5V to +34V, symmetrical supplies from 5V to 22V or asymmetrical supplies limited to a maximum differential voltage of 44V with a V+ max of 34V or a V- max of -25V. The four switches are bilateral, equally matched for AC or bidirectional signals. The ON resistance variation with analog signals is quite low over a 5V analog input range. The switches in the DG441 and DG442 are identical, differing only in the polarity of the selection logic. Features * ON Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . 85 * Low Power Consumption (PD) . . . . . . . . . . . . . . . <1.6mW * Fast Switching Action - tON (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns - tOFF (Max, DG441). . . . . . . . . . . . . . . . . . . . . . . . 120ns * Low Charge Injection * Upgrade from DG201A, DG202 * TTL, CMOS Compatible * Single or Split Supply Operation * Pb-Free Plus Anneal Available (RoHS Compliant) Applications * Audio Switching * Battery Operated Systems * Data Acquisition * Hi-Rel Systems * Sample and Hold Circuits * Communication Systems * Automatic Test Equipment Pinout DG441, DG442 (16 LD PDIP, SOIC, TSSOP) TOP VIEW IN1 1 D1 2 S1 3 V- 4 GND 5 S4 6 D4 7 IN4 8 16 IN2 15 D2 14 S2 13 V+ 12 NC 11 S3 10 D3 9 IN3 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2006. All Rights Reserved DG441, DG442 Ordering Information PART NUMBER DG441DJ DG441DJZ (Note) DG441DY DG441DY-T DG441DYZ (Note) DG441DYZ-T (Note) DG441DYZA (Note) DG441DYZA-T (Note) DG441DVZ (Note) DG441DVZ-T (Note) DG442DJ DG442DJZ (Note) DG442DY DG442DY-T DG442DYZ (Note) DG442DYZ-T (Note) DG442DVZ (Note) DG442DVZ-T (Note) PART MARKING DG441DJ DG441DJZ DG441DY DG441DY DG441DYZ DG441DYZ DG441DYZ DG441DYZ DG441DVZ DG441DVZ DG442DJ DG442DJZ DG442DY DG442DY DG442DYZ DG442DYZ DG442DVZ DG442DVZ TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 16 Ld SOIC Tape and Reel -40 to +85 16 Ld SOIC (Pb-free) 16 Ld PDIP 16 Ld PDIP* (Pb-free) 16 Ld SOIC PACKAGE PKG. DWG. # E16.3 E16.3 M16.15 M16.15 M16.15 M16.15 M16.15 M16.15 M16.173 M16.173 E16.3 E16.3 M16.15 M16.15 16 Ld SOIC (Pb-free) M16.15 M16.15 M16.173 M16.173 16 Ld SOIC Tape and Reel (Pb-free) -40 to +85 16 Ld SOIC (Pb-free) 16 Ld SOIC Tape and Reel (Pb-free) -40 to +85 -40 to +85 -40 to +85 -40 to +85 -40 to +85 16 Ld SOIC Tape and Reel -40 to +85 16 Ld TSSOP (Pb-free) 16 Ld TSSOP Tape and Reel (Pb-free) 16 Ld PDIP 16 Ld PDIP* (Pb-free) 16 Ld SOIC 16 Ld SOIC Tape and Reel (Pb-free) -40 to +85 16 Ld TSSOP (Pb-free) 16 Ld TSSOP Tape and Reel (Pb-free) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Functional Diagrams DG441 S1 IN1 D1 S2 IN2 D2 S3 IN3 D3 S4 IN4 D4 SWITCHES SHOWN FOR LOGIC "1" INPUT IN4 D4 IN3 D3 S4 IN2 D2 S3 IN1 D1 S2 DG442 S1 TRUTH TABLE LOGIC 0 1 VIN 0.8V 2.4V DG441 ON OFF DG442 OFF ON 2 FN3281.10 November 20, 2006 DG441, DG442 Schematic Diagram V+ (One Channel) S VINX V+ D GND 1 PER DIE COMMON TO EVERY CHANNEL V- Pin Descriptions PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SYMBOL IN1 D1 S1 VGND S4 D4 IN4 IN3 D3 S3 NC V+ S2 D2 IN2 Logic Control for Switch 1 Drain (Output) Terminal for Switch 1 Source (Input) Terminal for Switch 1 Negative Power Supply Terminal Ground Terminal (Logic Common) Source (Input) Terminal for Switch 4 Drain (Output) Terminal for Switch 4 Logic Control for Switch 4 Logic Control for Switch 3 Drain (Output) Terminal for Switch 3 Source (Input) Terminal for Switch 3 No Internal Connection Positive Power Supply Terminal (Substrate) Source (Input) Terminal for Switch 2 Drain (Output) Terminal for Switch 2 Logic Control for Switch 2 DESCRIPTION 3 FN3281.10 November 20, 2006 DG441, DG442 Absolute Maximum Ratings V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25V GND to V+ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+34V Digital Inputs, VS, VD (Note 1) . . . . . . . . (V-) -2V to (V+) + 2V or 30mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . 100mA Thermal Information Thermal Resistance (Typical, Note 2) JA (C/W) PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Maximum Junction Temperature (Plastic Packages) . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (SOIC and TSSOP- Lead Tips Only) *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Signal Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V (Max) Input Low Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8V (Max) Input High Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V (Min) Input Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20ns CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Signals on SX, DX or INX exceeding V+ or V- will be clamped by internal diodes. Limit forward diode current to maximum current ratings. 2. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications (Dual Supply) Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V, VANALOG = VS , VD , Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 3) TYP MAX UNITS PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF DG441 DG442 Charge Injection, Q (Figure 2) OFF Isolation (Figure 4) Crosstalk (Channel-to-Channel) (Figure 3) Source OFF Capacitance, CS(OFF) Drain OFF Capacitance, CD(OFF) Channel ON Capacitance, CD(ON) + CS(ON) DIGITAL INPUT CHARACTERISTICS Input Current VIN Low, IIL Input Current VIN High, IIH ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) RL = 1k, CL = 35pF, VS = 10V, (Figure 1) +25 - 150 250 ns +25 - 90 110 -1 60 -100 4 4 16 120 210 - ns ns pC dB dB pF pF pF CL = 1nF, VG = 0V, RG = 0 RL = 50, CL = 5pF, f = 1MHz +25 +25 +25 - f = 1MHz, VANALOG = 0 (Figure 5) +25 +25 +25 VIN Under Test = 0.8V, All Others = 2.4V VIN Under Test = 2.4V, All Others = 0.8V Full Full -0.5 -0.5 -0.00001 0.00001 0.5 0.5 A A Full IS = 10mA, VD = 8.5V, V+ = 13.5V, V- = -13.5V V+ = 16.5V, V- = -16.5V, VD = 15.5V, VS = 15.5V +25 +85 +25 +85 +25 +85 -15 -0.5 -5 -0.5 -5 -0.5 -10 50 0.01 0.01 0.08 - 15 85 100 0.5 5 0.5 5 0.5 10 V nA nA nA nA nA nA Source OFF Leakage Current, IS(OFF) Drain OFF Leakage Current, ID(OFF) V+ = 16.5V, V- = -16.5V, VS = VD = 15.5V Channel ON Leakage Current, ID(ON) + IS(ON) +25 +85 4 FN3281.10 November 20, 2006 DG441, DG442 Electrical Specifications (Dual Supply) Test Conditions: V+ = +15V, V- = -15V, VIN = 2.4V, 0.8V, VANALOG = VS , VD , Unless Otherwise Specified (Continued) TEST CONDITIONS TEMP (C) MIN (NOTE 3) TYP MAX UNITS PARAMETER POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, I- V+ = 16.5V, V- = -16.5V, VIN = 0V or 5V Full +25 Full -1 -5 -100 15 -0.0001 -15 100 - A A A A Ground Current, IGND Full Electrical Specifications PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q (Figure 2) (Single Supply) Test Conditions: V+ = 12V, V- = 0V, VIN = 2.4V, 0.8V, Unless Otherwise Specified TEST CONDITIONS TEMP (C) MIN (NOTE 3) TYP MAX UNITS RL = 1k, CL = 35pF, VS = 8V, (Figure 1) +25 +25 - 300 60 2 450 200 - ns ns pC CL = 1nF, VG = 6V, RG = 0 +25 ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON Resistance, rDS(ON) IS = 10mA, VD = 3V, 8V V+ = 10.8V Full +25 Full 0 100 12 160 200 V POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ Negative Supply Current, IV+ = 13.2V, V- = 0V, VIN = 0V or 5V Full +25 Full Ground Current, IGND NOTES: 3. Typical values are for DESIGN AID ONLY, not guaranteed nor production tested. Full -1 -100 -100 15 -0.0001 -0.0001 -15 100 A A A A 5 FN3281.10 November 20, 2006 DG441, DG442 Test Circuits and Waveforms VO is the steady state output with the switch on. Feedthrough via switch capacitance may result in spikes at the leading and trailing edge of the output waveform. 3V LOGIC INPUT 50% 0V tOFF SWITCH INPUT VS VO SWITCH OUTPUT 0V tON 80% 80% LOGIC INPUT 3V tr < 20ns tf < 20ns SWITCH INPUT S1 IN1 RL GND VCL V+ D1 VO NOTE: Logic input waveform is inverted for switches that have the opposite logic sense. FIGURE 1A. MEASUREMENT POINTS Repeat test for Channels 2, 3 and 4. For load conditions, see Specifications. CL includes fixture and stray capacitance. RL V O = V S ----------------------------------R L + r DS ( ON ) FIGURE 1B. TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ SWITCH OUTPUT VO RG D1 VO INX (DG441) OFF ON OFF VG VCL VIN = 3V OFF GND INX (DG442) OFF ON Q = VO x CL FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION FIGURE 2B. TEST CIRCUIT C V+ +15V C SIGNAL GENERATOR 10dBm V+ +15V SIGNAL GENERATOR 10dBm VS VD 50 VS 0V, 2.4V IN1 IN2 0V, 2.4V INX 0V, 2.4V ANALYZER RL VD V-15V C NC ANALYZER RL VD V-15V C GND GND FIGURE 3. CROSSTALK TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT 6 FN3281.10 November 20, 2006 DG441, DG442 Test Circuits and Waveforms (Continued) C V+ +15V VS IMPEDANCE ANALYZER VD f = 1MHz V-15V C INX 0V, 2.4V GND FIGURE 5. SOURCE/DRAIN CAPACITANCES TEST CIRCUIT Application Information GAIN ERROR IS DETERMINED ONLY BY THE RESISTOR TOLERANCE. OP AMP OFFSET AND CMRR WILL LIMIT ACCURACY OF CIRCUIT. +15V -15V FET INPUT 7 4 OP AMP 3 6 2 +15V 13 2 GAIN1 AV = 1 GAIN2 AV = 10 GAIN3 AV = 20 GAIN4 AV = 100 1 15 16 10 9 7 8 V4 -15V GND 5 6 R4 1k 11 R3 4k 14 +15V R2 5k VIN + 1/4 DG442 SX DX + CH 3 R1 90k VIN VOUT - VOUT - INX 1 = SAMPLE 0 = HOLD -15V V OUT R1 + R2 + R3 + R4 --------------- = ------------------------------------------------ = 100 with SW 4 closed V IN R4 FIGURE 6. PRECISION WEIGHTED RESISTOR PROGRAMMABLE GAIN AMPLIFIER FIGURE 7. OPEN LOOP SAMPLE AND HOLD 7 FN3281.10 November 20, 2006 DG441, DG442 Typical Performance Curves 100 5V 80 60 +125C rDS(ON) () rDS(ON) () 60 8V 10V 12V 40 15V 20V 20 10 0 -20 0 -15 50 40 30 20 0C -40C -55C +85C +25C 80 70 V+ = +15V V- = -15V 0 VD (V) 20 0 VD (V) 15 FIGURE 8. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE 140 120 100 rDS(ON) () 80 60 40 20 0 0C -40C -55C 300 FIGURE 9. rDS(ON) vs VD AND TEMPERATURE V+ = +12V V- = 0V +125C +85C V- = 0V 250 V+ = +5V 200 +25C rDS(ON) () 150 +8V 100 +10V +12V +15V 50 +20V 0 6 VD (V) 12 0 0 10 VD (V) 20 FIGURE 10. rDS(ON) vs VD AND TEMPERATURE (SINGLE 12V SUPPLY) 105 104 103 IIN (pA) 102 FIGURE 11. rDS(ON) vs VD AND SINGLE SUPPLY VOLTAGE 105 104 103 I+, I-, IGND (nA) 102 10 1 -(I-) 0.1 I+, IGND 10 1 0.01 0.001 -55 0.1 -55 0 50 TEMPERATURE (C) 100 125 0 50 TEMPERATURE (C) 100 125 FIGURE 12. INPUT CURRENT vs TEMPERATURE FIGURE 13. SUPPLY CURRENT vs TEMPERATURE 8 FN3281.10 November 20, 2006 DG441, DG442 Typical Performance Curves 140 120 100 80 (-dB) 60 40 20 0 100 V+ = +15V V- = -15V PGEN = 10dBm 1k 10k 100k FREQUENCY (Hz) 1M 10M OFF ISOLATION (Continued) 50 40 30 20 Q (pC) 10 0 -10 -20 -30 -10 CL = 10nF CL = 1nF CL = 10nF CL = 1nF V+ = +15V V- = -15V SINGLE SUPPLY V+ = +12V V- = 0V CROSSTALK -5 0 VS (V) 5 10 FIGURE 14. CROSSTALK AND OFF ISOLATION vs FREQUENCY 160 140 120 tON, tOFF (ns) tON, tOFF (ns) 100 80 60 40 20 tOFF (DG441) tON (DG442) tOFF (DG442) V+ = +15V V- = -15V FIGURE 15. CHARGE INJECTION vs SOURCE VOLTAGE 160 tON (DG441) 140 tON 120 100 80 tOFF 60 40 20 2 3 VIN (V) 4 5 10 12 14 16 18 SUPPLY VOLTAGE (V) 20 22 FIGURE 16. SWITCHING TIMES vs INPUT VOLTAGE FIGURE 17. SWITCHING TIME vs POWER SUPPLY VOLTAGE (DG441) 2.4 20 IS(OFF) , ID(OFF) 0 -20 IS, ID (pA) VIN (V) 1.6 -40 IS(ON) + ID(ON) -60 V+ = +15V V- = -15V FOR I(OFF) , VD = -VS 0.8 -80 -100 -15 0 -10 -5 0 VS , VD (V) 5 10 15 0 5 10 15 SUPPLY VOLTAGE (V) 20 FIGURE 18. LEAKAGE CURRENT vs ANALOG VOLTAGE FIGURE 19. SWITCHING THRESHOLD vs SUPPLY VOLTAGE 9 FN3281.10 November 20, 2006 DG441, DG442 Typical Performance Curves 25 V+ = +15V V- = -15V (Continued) 20 V+ = +12V V- = 0V CS(ON) + CD(ON) 15 20 CS(ON) + CD(ON) CS , D (pF) CS , D (pF) 15 10 10 CS(OFF) , CD(OFF) 5 5 CS(OFF) , CD(OFF) 0 -15 -10 -5 0 VA (V) 5 10 15 0 0 6 VA (V) 12 FIGURE 20. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE 10 IS(OFF) , ID(OFF) 0 FIGURE 21. SOURCE/DRAIN CAPACITANCE vs ANALOG VOLTAGE (SINGLE 12V SUPPLY) 400 V+ = +12V V- = 0V 300 tON, tOFF (ns) tON (DG442) 200 tON (DG441) IS , ID (pA) -10 -20 IS(ON) + ID(ON) -30 V+ = +12V V- = 0V FOR ID , VS = 0 FOR IS , VD = 0 0 6 VS , VD (V) 12 100 tOFF (DG442) -40 0 2 3 VIN (V) 4 tOFF (DG441) 5 FIGURE 22. SOURCE/DRAIN LEAKAGE CURRENTS (SINGLE 12V SUPPLY) 500 V- = 0V 400 tON tON, tOFF (ns) 300 FIGURE 23. SWITCHING TIME vs INPUT VOLTAGE (SINGLE 12V SUPPLY) 200 100 tOFF 0 8 10 12 14 16 18 POSITIVE SUPPLY (V) 20 22 FIGURE 24. SWITCHING TIME vs SINGLE SUPPLY VOLTAGE (DG441) 10 FN3281.10 November 20, 2006 DG441, DG442 Die Characteristics DIE DIMENSIONS: 2160m x 1760m x 485m METALLIZATION: Type: SiAl Thickness: 12kA 1kA PASSIVATION: Type: Nitride Thickness: 8kA 1kA WORST CASE CURRENT DENSITY: 9.1 x 104 A/cm2 Metallization Mask Layout DG441, DG442 D1 (2) IN1 (1) IN2 (16) (15) D2 S1 (3) (14) S2 V- (4) (13) V+ SUBSTRATE GND (5) (12) NC (11) S3 S4 (6) (7) D4 (8) IN4 (9) IN3 (10) D3 11 FN3281.10 November 20, 2006 DG441, DG442 Dual-In-Line Plastic Packages (PDIP) N INDEX AREA E1 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 -CA2 L A1 A C L E E16.3 (JEDEC MS-001-BB ISSUE D) 16 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E E1 e eA eB L N MIN 0.015 0.115 0.014 0.045 0.008 0.735 0.005 0.300 0.240 MAX 0.210 0.195 0.022 0.070 0.014 0.775 0.325 0.280 MILLIMETERS MIN 0.39 2.93 0.356 1.15 0.204 18.66 0.13 7.62 6.10 MAX 5.33 4.95 0.558 1.77 0.355 19.68 8.25 7.11 NOTES 4 4 8, 10 5 5 6 5 6 7 4 9 Rev. 0 12/93 e eA eC C C A BS eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 0.100 BSC 0.300 BSC 0.115 16 0.430 0.150 2.54 BSC 7.62 BSC 2.93 16 10.92 3.81 12 FN3281.10 November 20, 2006 DG441, DG442 Small Outline Plastic Packages (SOIC) N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM M16.15 (JEDEC MS-012-AC ISSUE C) 16 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A L MILLIMETERS MIN 1.35 0.10 0.33 0.19 9.80 3.80 MAX 1.75 0.25 0.51 0.25 10.00 4.00 NOTES 9 3 4 5 6 7 8 Rev. 1 6/05 MIN 0.0532 0.0040 0.013 0.0075 0.3859 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.3937 0.1574 A1 B C D E A1 0.10(0.004) C e H h L N 0.050 BSC 0.2284 0.0099 0.016 16 0 8 0.2440 0.0196 0.050 1.27 BSC 5.80 0.25 0.40 16 0 6.20 0.50 1.27 e B 0.25(0.010) M C AM BS NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 13 FN3281.10 November 20, 2006 DG441, DG442 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E E1 -B1 2 3 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 L 0.25(0.010) M GAUGE PLANE BM M16.173 16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D E1 A2 c 0.10(0.004) C AM BS MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 6.25 0.50 16 8o 0o 8o MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 6.50 0.70 NOTES 9 3 4 6 7 Rev. 1 2/02 MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 0.246 0.020 16 0o MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 0.256 0.028 e b 0.10(0.004) M A1 e E L N 0.026 BSC 0.65 BSC NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN3281.10 November 20, 2006 |
Price & Availability of DG441DY-T
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